1. Field of the Invention
The invention relates to an improved configuration memory structure using one or more distributed buffers.
2. Description of the Related Art
Field programmable gate arrays (FPGAs) are semi-custom devices, which contain a fixed set of gate structures, which can be interconnected in a number of ways to implement a desired logic function by programming the interconnect pattern electrically.
FPGAs generally include an array of programmable logic blocks (PLB). A PLB is also called a configurable logic block (CLB) or a configurable logic element (CLE) or programmable function unit (PFU). Each PLB contains one or more input lines, one or more output lines, one or more latches and one or more look up tables (LUT). The LUT can be programmed to perform various functions including general combinatorial or control logic or a data path between the input and output lines. The LUT thus determines whether the respective PLB implements a general logic, or a special mode function such as an adder, a subtractor, a counter or a register.
The configuration values stored in static random access memory (SRAM) latches program the connections or select the functionality for LUT. These SRAM cells are volatile in nature to provide reconfiguration flexibility. Using this flexibility, a number of iterations for design implementation can be tried with an FPGA device to achieve the system specifications. This technique is very useful for prototyping a new design during a developing and debugging stage, which significantly reduces developing and manufacturing expenses and time. The verification and debugging of the implemented design is done by reading the configuration data and comparing the same with the configuration bits. The configurable memory cells of a PLD are typically arranged in an array and loaded using serial bit streams of configuration data.
FIG. 1 illustrates a configuration memory array according to the prior art. Configuration memory array 150 comprises memory cells 100-xy where x and y correspond to the column and row location respectively of each configuration memory cell.
The configuration of data into the configuration memory array 150 is achieved by shifting the bit stream of configuration data. This frame of data from configuration shift register DATA REG 130 is released in parallel through horizontal data lines 111 to 115 into a column of configuration memory cells enabled by horizontal shift register SELECT REG 140. The row is addressed by shifting a high/low bit to one of the selected vertical lines 105–110 via the flip-flop array of horizontal shift register SELECT REG 140 using one shift per frame. The loading of data is therefore performed in a Serial In Parallel Out (SIPO) mode. In this way, configuration cells from 100-00 to 100_0y are loaded at the same time using their respective data lines 111 to 115 by enabling their common clock line 105. And similarly, each column of configuration cells will be loaded by enabling their respective clock line 105–110 one at a time.
FIG. 2 is a schematic diagram of a portion of an FPGA 200 in accordance with one embodiment of U.S. Pat. No. 6,057,704 entitled “Partially Reconfigurable FPGA And Method Of Operating The Same”. FPGA 200 includes frame register 210, row decoder 209, write buffers 201–203, read buffers 204–206, row access transistors 211–213, row lines 221–223 and associated parasitic capacitances 221C–223C, row pull-up transistors 291–293, column select lines 231–232, cell access transistors 241–246, configuration memory cells 251–256, column select circuits 261–262, column voltage line 270 and column voltage circuit 280. Column select circuits 261 and 262 include inverters 263–264, p-channel field effect transistors (FETs) 265–266 and n-channel FETs 267–268. Column voltage circuit 280 includes p-channel FETs 271–272 and inverter 273. Together, frame register 210, row decoder 209, write buffers 201–203, read buffers 204–206 and row access transistors 211–213 form a row access circuit. Similarly, column voltage circuit 280 and column select circuits 261 and 262 form a column access circuit.
Frame register 210 receives and stores a plurality of configuration data values. These configuration data values are typically received from an external source, but can also be received from an internal source. The configuration data values are transferred from frame register 210 to an array of configuration memory cells, which includes configuration memory cells 251–256. The configuration data values can be written from frame register 210 to the array of configuration memory cells on a full column or partial column basis. The configuration data values can be read from the array to frame register 210 on a full column basis.
The configuration data values stored in configuration memory cells 251–256 are provided to control predetermined programmable interconnection points (PIPs) and define lookup table contents. The PIPs and lookup tables, in response to the configuration data values, configure the FPGA. The configuration data values can also be read from the configuration memory cells 251–256 to the frame register 210.
A pair of CMOS inverters, which are cross-coupled to form a latch, form each of configuration memory cells 251–256. The configuration memory cells 251–256 are arranged in an array of rows and columns. Thus, configuration memory cells 251 and 252 are in a first row of the array, configuration memory cells 253 and 254 are in a second row of the array, and configuration memory cells 255 and 256 are in the last row of the array. Similarly, configuration memory cells 251, 253 and 255 are in a first column of the array and configuration memory cells 252, 254 and 256 are in a second column of the array. Frame register 210 can be located on one side of the array of configuration memory cells or frame register 210 can extend through a central location of the array of configuration memory cells, or there can be more than one frame register in FPGA 200.
Each of configuration memory cells 251–256 is coupled to one of row lines 221–223 through an associated cell access transistor 241–246. The source of each cell access transistor is coupled to an associated row line, and the drain of each cell access transistor is coupled to an associated configuration memory cell. Row lines 221–223, in turn, are coupled to associated write buffers 201–203, respectively, through associated row access transistors 211–213, respectively. Row lines 221–223 are also coupled to associated read buffers 204–206, respectively. Row lines 221–223 are relatively long lines, which extend substantially across the width of FPGA 200, and connect to diffusion regions of many cell access transistors. As a result, each of the row lines 221–223 has a significant associated parasitic capacitance. The capacitances 221C–223C associated with row lines 221–223 are shown in dashed lines in FIG. 2.
Each of write buffers 201–203 and read buffers 204–206 is coupled to frame register 210 as illustrated. The gate of each of the row access transistors 211–213 has a dedicated connection to row decoder 209. As a result, any number of the row access transistors 211–213 can be enabled at any given time. The row decoder 209 helps to enable the partial reconfiguration of FPGA 200. Pull-up transistors 291–293 are turned on by asserting an active low PRECHG signal, thus pulling lines 221–223 high.
The cell access transistors associated with each column of the array of configuration memory cells are connected to an associated column select line. Thus, the gates of cell access transistors 241, 243 and 245 are coupled to column select line 231. Similarly, the gates of cell access transistors 242, 244 and 246 are coupled to column select line 232.
Each of the column select lines 231–232, in turn, is connected to an associated column select circuit 261–262, respectively. Column select circuits 261 and 262 are included so that a choice of voltages (i.e., a read voltage or a write voltage) can be provided from column voltage line 270 to column select lines 231 and 232. Column select circuit 261 includes an inverter 263, which is coupled to receive a column select signal CS1. The output terminal of inverter 263 is coupled to the gates of p-channel FET 265 and n-channel FET 267. The drain and source regions of n-channel FET 267 are connected to column select line 231 and ground (the off voltage), respectively. The source and drain regions of p-channel FET 265 are coupled to column voltage line 270 and column select line 231, respectively. Column select circuit 262 is connected to column select line 232 in a similar manner.
Column voltage line 270 is coupled to column voltage supply circuit 280 as illustrated. Thus, the drains of p-channel FETs 271 and 272 are coupled to column voltage line 270. The sources of p-channel FETs 271 and 272 are coupled to receive voltages of 5 Volts and 2.5 Volts, respectively. The Vcc supply voltage of FPGA 200 is 5 Volts. Both the read voltage and the write voltage are greater than the threshold voltage of the cell access transistors, and the write voltage is greater than the read voltage. If the chip is designed to operate with a supply voltage of less than 5 Volts, the read and write voltages are correspondingly lower.
As there are a large number of configuration columns in a high density FPGA core; the data lines have significant capacitance value. For ensuring the proper and fast write operation on configuration latches, there is a need to place write buffers at intermediate stages on data lines.
For configuration readback, all the data lines are precharged to logic ‘1’ and a low voltage is applied to the selected column line. The voltage should be low enough so that it does not disturb the latch value. The limitation of this scheme is that it requires generating another voltage supply for read operation. The design is sensitive to noise on the column voltage line, which may disturb the latched value. For high-density devices, the presence of intermediate write buffers on data lines limits the readback operation. Therefore, there is a need for a scheme for a single voltage readback operation without disturbing latch value for high-density device with intermediate data buffers.